Dr. Soorya Krishna K.
Education Details
| Degree | Specialization | University | Year |
| B.E | B.E- Electronics and Communication Engineering | Kuvempu, Shivmogga | 1999 |
| M.Tech | M.Tech – Digital Electronics and Communication | VTU, Belgavia | 2003 |
| Ph.D. | VLSI | NITK | 2013 |
Experience Details
| Field | Designation | Workplace | From | To |
| Teaching | Professor | SIT, Mangalore | 23-01-2013 | Till Date |
| Teaching | Asst. Professor | St. Joseph Engineering College, Mangalore | 20-07-2003 | 22-01-2013 |
| Research | Research Scholar | NITK, Surathkal | 20-7-2007 | 20-7-2010 |
Subjects Handled
| M.Tech - Digital VLSI Circuits, Design of Analog and Mixed Mode VLSI Circuit, RF CMOS VLSI, Synthesis and Optimization of Digital Circuits |
| B.E - Analog Electronic Circuits, Linear Integrated Circuits Microelectronic Circuits, CMOS VLSI, Fundamentals of HDL, Digital Design using Verilog |
Area of Interest
| High Speed Interconnects, Low power VLSI, AI, IoT |
Publications in Journals
| Inter National Journals | |
| 1 | Soorya Krishna K, Pramod M and M.S. Bhat, “Modeling of Single, Coupled, L and T type interconnects using State Space approach ”, International Journal of Signal and Imaging Systems Engineering from Inderscience Publishers, vol. 2, no. 4, pp. 216-223, ISSN: 1748-0701, October-December 2009. |
| 2 | Soorya Krishna K and M.S. Bhat, “Minimization of Via Induced Signal Reflection in On-Chip High Speed Interconnect Lines”, Circuits, Systems and Signal Processing from Springer publications, vol. 31, no. 2, pp. 689-702, ISSN: 1531-5878, April 2012. |
| 3 | Soorya Krishna K and M.S. Bhat, “Impedance Matching in Multi-Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications”, International Journal of Computer and Electrical Engineering, vol. 4, no. 3, pp. 345-349, May 2013. |
| 4 | Colin David Karat and Soorya Krishna K, “ Simulation of 8T SRAM Array for Low Power Sensor Application”, IJCA Proceedings on National Conference “Electronics, Signals, Communication and Optimization”, No. 3, 2015. |
| 5 | Gayathri Prabhu M , Soorya Krishna K, Apoorva C and Apoorva,“Smart Surveillance Vigilant Detection and Notification System”, Asian Journal of Convergence in Technology, Volume IV 2018, Issue II, ISSN NO: 2350-1146 I.F-5.11.Mahaveera K, Jewel Mercy Fernandes, and Soorya Krishna K, “Design of Flash ADC using NAND based Fat Tree Encoder”, First International Conference on Advances in Electrical and Computer Technologies 2019 (ICAECT-2019), Coimbatore, Tamilnadu, India, 26-27, April 2019 |
| 6 | Mahaveera K, Jewel Mercy Fernandes, Soorya Krishna K, “8-Bit SAR ADC with Double-tail Dynamic Latch Comparator”, ‘International Journal of Engineering and Advanced Technology (IJEAT)’, Volume-9 Issue-1, October 2019. |
Paper presented in conferences
| Inter National conferences | |
| 1 | Soorya Krishna K, Pramod M and M.S. Bhat, “Estimation of Interconnect Metrics using State Space Approach”, International Conference on Industrial and Information Systems (ICIIS-2010) at NITK, Surathkal, pp. 255-260, IEEE, 2010. |
| 2 | Soorya Krishna K and M.S. Bhat, “Performance enhancement in high speed on-chipinterconnect lines”, International Conference on Industrial and Information Systems (ICIIS-2010) at NITK, Surathkal, pp. 228-233, IEEE, 2010. |
| 3 | Soorya Krishna K and M.S. Bhat, “Crosstalk Estimation in Coupled Interconnect lines using State Space Approach”, in 14th IEEE/VDAT 2010 VLSI Design and Test Symposium at Chitkara University, Himachal Pradesh, July 2010. |
| 4 | Soorya Krishna K and M.S. Bhat, “Impedance Matching for the Reduction of Via Induced Signal Reflection in On-Chip High Speed Interconnect Lines”, International Conference on Computer and Communication Technology (ICCCCT-2010) at St. Xavier Catholic College of Engineering, Kanyakumari, pp. 120-125, IEEE, 2010. |
| 5 | Soorya Krishna K and M.S. Bhat, “Impedance Matching in Multi-Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications”, Third International Conference on Signal Acquisition and Processing in Singapore, February 26-28, pp. 250 - 54, IEEE, 2011. |
| 6 | Colin David Karat and Soorya Krishna K, “Design of SRAM Array using 8T Cell for Low Power Sensor Application”, 5th Nirma University International Conference on Engineering (NUICONE), 26 Nov - 28 Nov 2015. |
| 7 | Mahaveera K, Jewel Mercy Fernandes, and Soorya Krishna K, “Design of Flash ADC using NAND based Fat Tree Encoder”, First International Conference on Advances in Electrical and Computer Technologies 2019 (ICAECT-2019), Coimbatore, Tamilnadu, India, 26-27, April 2019 |
| 8 | Jewel Mercy Fernandes, Mahaveera K and Soorya Krishna K, “Design of Double-tail Dynamic Latch Comparator for Low Power Application”, International Conference on Intelligent Sustainable Systems (ICISS 2019), ISBN: 978-1-5386-7798-8. |
Workshop/Seminar attended/Guest lectures delivered
| 1 | Attended 5 Days Online FDP Program on “Low Power VLSI Design” from 20-4-2020 to 24-04-2020 from National Institute of Technical Teachers Training and Research, Chandigarh. |
| 2 | Attended 5 Days Online FDP Program on “IoT” from 10-4-2020 to 14-04-2020 from National Institute of Technical Teachers Training and Research, Chandigarh. |
| 3 | Attended 5 Days Training Program on “Outcome Based Education and NBA Accreditation” from 30-12-2019 to 03-01-2020, at MITE, Mangaluru in association with VTU-TEQIP 1.3. |
| 4 | Attended 3 day Workshop on "Electronic System Design for Manufacturing using EDA Tools” from 11-12-2019 to 13-12-2019 at SITE, Mangaluru in association with BITES. |
| 5 | Attended 5 Days FDP on “Embedded Systems, IOT and Sensor Application with Blended Learning Concepts” from 2-7-2019 to 6-7-2019 at Vidyavardhaka College of ngineering, Mysuru in association with Teaching Learning Centre, Coimbatore Institute of Technology. |
| 6 | Attended 6 Days FDP on “Thin Films and its Applications” from 04-02-2019 to 09-02-2019 conducted at RV College of Enineering, Bengaluru. |
| 7 | Attended 1 Day workshop on “VLSI Test” held at NITK Surathkal on 30-3-2019 |
| 8 | Attended 3 day Training program on "End-to-End IoT Design" from 29-09-to 01-10-2018 at NITK Surathkal. |
| 9 | Attended 5 days VGST Sponsored FDP program on “Embedded Systems for Commucation Applications” from 19 to 23 June 2018 at NMAMIT, Nitte. |
| 10 | Attended 4 days VGST sponsored FDP program on “Sytem Design using System Verilog” from 24-4-2018 to 27-4-2018 organized by Department of VLSI Design and embedded Sytem, center of PG studies, VTU Belgaum. |
| 11 | Attended 5 days Short Term course on “Mathematical Methods and Solid State Physics” conducted during 24-28 July 2017 at IISC, Bangalore. |
| 12 | Completed NPTEL course on “Analog Circuits” in Feb-April 2020(8 Week course). |
| 13 | Completed NPTEL course on “Switching Circuits and Logic Design” with 65% in July-Oct 2019(12 Week course). |
| 14 | Completed NPTEL course on “CMOS Digital VLSI Design” with 73% in Feb- Apr 2019(8 Week course). |
| 15 | Going to Complete Online Course on “Hardware Description Languages for FPGA Design" in Coursera in 2020 |
Projects Guided
| B.E projects | 10 |
| M.Tech projects | 4 |
| PhD projects | 1 |
Membership in professional bodies
| ISTE |
Departmental Responsibilities
| 1 | Head of the ECE Department |
| 2 | NAAC Criteria 5 |
| 3 | ISAP College Coordinator |
| 4 | EDC Cell Incharge |
| 5 | NPTEL Department Incharge |
