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Soorya Krishna K, Pramod M and M.S. Bhat, “Modeling of Single, Coupled, L and T type interconnects using State Space approach ”, International Journal of Signal and Imaging Systems Engineering from Inderscience Publishers, vol. 2, no. 4, pp. 216-223, ISSN: 1748-0701, October-December 2009.
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Soorya Krishna K and M.S. Bhat, “Minimization of Via Induced Signal Reflection in On-Chip High Speed Interconnect Lines”, Circuits, Systems and Signal Processing from Springer publications, vol. 31, no. 2, pp. 689-702, ISSN: 1531-5878, April 2012.
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Soorya Krishna K and M.S. Bhat, “Impedance Matching for the Reduction of Via Induced Signal Reflection in On-Chip High Speed Interconnect Lines”, International Conference on Computer and Communication Technology (ICCCCT-2010) at St. Xavier Catholic College of Engineering, Kanyakumari, pp. 120-125, IEEE, 2010.
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Soorya Krishna K and M.S. Bhat, “Impedance Matching in Multi- Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications”, Third International Conference on Signal Acquisition and Processing in Singapore, February 26-28, pp. 250 -54, IEEE, 2011.
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Soorya Krishna K and M.S. Bhat, “Impedance Matching in Multi-Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications”, International Journal of Computer and Electrical Engineering, vol. 4, no. 3, pp. 345-349, May 2013.
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Colin David Karat and Soorya Krishna K, “ imulation of 8T SRAM Array for Low Power Sensor Application”, IJCA Proceedings on National Conference “Electronics, Signals, Communication and Optimization”, No. 3, 2015.
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Colin David Karat and Soorya Krishna K, “Design of SRAM Array using 8T Cell for Low Power Sensor Application”, 5th Nirma University International Conference on Engineering (NUICONE), 26 Nov – 28 Nov 2015.